| ... | ... | @@ -41,7 +41,7 @@ This wiki page gives an overview of the various server machines offered by the A |
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| architecture | [Nehalem](https://en.wikipedia.org/wiki/Nehalem_(microarchitecture)) | [Nehalem](https://en.wikipedia.org/wiki/Nehalem_(microarchitecture)) | [Skylake-H](https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client)) | [Skylake-SP](https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(server)) | [Skylake-SP](https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(server)) | [Skylake-SP](https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(server)) | [Knights Landing](https://en.wikichip.org/wiki/intel/microarchitectures/knights_landing) |
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| vector instructions | SSE4.2 | SSE4.2 | AVX2 | AVX-512 | AVX-512 | AVX-512 | AVX-512 |
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| cores per socket | 4 | 4 | 4 | 8 | 16 | 24 | 64 |
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| SMT | | | 2 threads per core | | | | |
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| simultaneous multithreading | | | 2 threads per core | | | | |
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| base frequency | 2.0 GHz | 2.4 GHz | 3.5..3.9 GHz | 2.4..3.0 GHz | 2.8..3.7 GHz | 3.4..3.7 GHz | 1.3..1.5 GHz |
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| AVX2 frequency | | | 3.5..3.9 GHz | 2.1..2.9 GHz | 2.4..3.6 GHz | 3.0..3.6 GHz | 1.1 GHz |
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| AVX-512 frequency | | | | 1.3..1.8 GHz | 1.9..3.5 GHz | 2.5..3.5 GHz | 1.1 GHz |
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| ... | ... | @@ -60,14 +60,15 @@ instruction set used. A tabular overview can be found on the WikiChip pages link |
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value ranges given in the table ("A..B GHz") state the clock frequencies for single-core load and
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full load.
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Simultaneous multithreading ("hyperthreading") is enabled on the mp-media* machines and disabled
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on all other machines.
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[Simultaneous multithreading](https://en.wikipedia.org/wiki/Simultaneous_multithreading) (also
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known as "hyperthreading") is enabled on the mp-media* machines and disabled on all other
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machines.
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eDRAM refers to the Embedded DRAM in the Skylake-H CPU, a memory side cache shared between CPU
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and GPU, cf.
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[https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client)](https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client)#eDRAM_architectural_changes).
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[https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client)#eDRAM_architectural_changes](https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client)#eDRAM_architectural_changes).
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HBM is the configurable high-bandwidth memory available on the Knights Landing CPUs, cf.
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HBM refers to the configurable high-bandwidth memory available on the Knights Landing CPUs, cf.
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[https://colfaxresearch.com/knl-mcdram/](https://colfaxresearch.com/knl-mcdram/).
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| ... | ... | @@ -75,10 +76,10 @@ HBM is the configurable high-bandwidth memory available on the Knights Landing C |
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| measure | Xeon E5504 | Xeon E5530 | Xeon E3-1585 | Xeon Silver 4110 | Xeon Gold 6130 | Xeon Platinum 8168 | Xeon Phi 7210 |
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| ---------------------------- | ----------- | ----------- | ---------------- | ---------------- | ---------------- | ------------------ | ---------------- |
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| L1 read per core | | | f/GHz × 128 GB/s | f/GHz × 128 GB/s | f/GHz × 128 GB/s | f/GHz × 128 GB/s | f/GHz × 128 GB/s |
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| L1 write per core | | | f/GHz × 64 GB/s | f/GHz × 64 GB/s | f/GHz × 64 GB/s | f/GHz × 64 GB/s | f/GHz × 64 GB/s |
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| L1 read+write per core | | | f/GHz × 192 GB/s | f/GHz × 192 GB/s | f/GHz × 192 GB/s | f/GHz × 192 GB/s | f/GHz × 192 GB/s |
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| L2 per core | | | f/GHz × 64 GB/s | f/GHz × 64 GB/s | f/GHz × 64 GB/s | f/GHz × 64 GB/s | f/GHz × 64 GB/s |
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| L1 read per core | | | $`f/\mathrm{GHz} \times 128 \mathrm{GB}/\mathrm{s}`$ | $`f`$/GHz × 128 GB/s | $`f`$/GHz × 128 GB/s | $`f`$/GHz × 128 GB/s | $`f`$/GHz × 128 GB/s |
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| L1 write per core | | | $`f`$/GHz × 64 GB/s | $`f`$/GHz × 64 GB/s | $`f`$/GHz × 64 GB/s | $`f`$/GHz × 64 GB/s | $`f`$/GHz × 64 GB/s |
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| L1 read+write per core | | | $`f`$/GHz × 192 GB/s | $`f`$/GHz × 192 GB/s | $`f`$/GHz × 192 GB/s | $`f`$/GHz × 192 GB/s | $`f`$/GHz × 192 GB/s |
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| L2 per core | | | $`f`$/GHz × 64 GB/s | $`f`$/GHz × 64 GB/s | $`f`$/GHz × 64 GB/s | $`f`$/GHz × 64 GB/s | $`f`$/GHz × 64 GB/s |
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| eDRAM, single-threaded | | | | | | | |
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| eDRAM, concurrent | | | | | | | |
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| HBM, single-threaded | | | | | | | |
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| ... | ... | @@ -86,9 +87,9 @@ HBM is the configurable high-bandwidth memory available on the Knights Landing C |
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| DRAM, single-threaded | | | 17.1 GB/s | 19.2 GB/s | 21.3 GB/s | 21.3 GB/s | |
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| DRAM, concurrent, per socket | | | 34.1 GB/s | 115.2 GB/s | 128 GB/s | 128 GB/s | ~90 GB/s |
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Note that all bandwidth indications use decimal unit prefixes, i.e. 1 GB = $10^9$ B.
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Note that all bandwidth indications use decimal unit prefixes, i.e. 1 GB = 10⁹ B.
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The cache bandwidths scale with the clock frequency $f$ which depends on the number of cores
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The cache bandwidths scale with the clock frequency $`f`$ which depends on the number of cores
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under load and the instruction set used. Computations are based on the number of 64B cache lines
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the CPUs can fetch or store in each cycle.
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| ... | ... | |
