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| `mp-media2` | Intel Xeon E3-1585 v5 | 3.5..3.9 GHz | 4 | Skylake-H | 64 GiB | Intel Iris Pro P580 | 1.6 TB | |
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| `mp-media3` | Intel Xeon E3-1585 v5 | 3.5..3.9 GHz | 4 | Skylake-H | 64 GiB | Intel Iris Pro P580 | | |
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| `mp-media4` | Intel Xeon E3-1585 v5 | 3.5..3.9 GHz | 4 | Skylake-H | 64 GiB | Intel Iris Pro P580 | | |
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| `mp-knl1` | Intel Xeon Phi 7210 | 1.3..1.5 GHz | 64 | Knights Landing | 96 GiB | | | Quadrant, Cache |
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| `mp-knl2` | Intel Xeon Phi 7210 | 1.3..1.5 GHz | 64 | Knights Landing | 96 GiB | | | Hemisphere, Cache |
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| `mp-knl3` | Intel Xeon Phi 7210 | 1.3..1.5 GHz | 64 | Knights Landing | 96 GiB | | | All2All, Cache |
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| `mp-knl4` | Intel Xeon Phi 7210 | 1.3..1.5 GHz | 64 | Knights Landing | 96 GiB | | | SNC, Cache |
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| `mp-knl1` | Intel Xeon Phi 7210 | 1.3..1.5 GHz | 64 | Knights Landing | 96 GiB | | | SNC4, Cache |
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| `mp-knl2` | Intel Xeon Phi 7210 | 1.3..1.5 GHz | 64 | Knights Landing | 96 GiB | | | SNC4, Cache |
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| `mp-knl3` | Intel Xeon Phi 7210 | 1.3..1.5 GHz | 64 | Knights Landing | 96 GiB | | | SNC4, Cache |
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| `mp-knl4` | Intel Xeon Phi 7210 | 1.3..1.5 GHz | 64 | Knights Landing | 96 GiB | | | SNC4, Cache |
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| `mp-process01` | Intel Xeon E5504 | 2.0 GHz | 4 | Nehalem | 8 GiB | NVIDIA GeForce GTX 1070 | | |
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| `mp-process02` | Intel Xeon E5504 | 2.0 GHz | 4 | Nehalem | 8 GiB | NVIDIA GeForce GTX 1070 | | |
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| `mp-process03` | Intel Xeon E5504 | 2.0 GHz | 4 | Nehalem | 8 GiB | NVIDIA GeForce GTX 1070 | | |
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- Cache and DRAM capacities are given with binary unit prefixes, i.e. 1 GiB = 2³⁰ B.
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- I/O storage device capacities are given with decimal unit prefixes, i.e. 1 TB = 10¹² B.
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- Cf. [https://colfaxresearch.com/knl-numa/](https://colfaxresearch.com/knl-numa/) and [https://colfaxresearch.com/knl-mcdram/](https://colfaxresearch.com/knl-mcdram/) to learn about clustering modes and HBM modes on Knights Landing CPUs.
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## CPU architecture overview
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cores under load and the instruction set used.
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- Cache bandwidths are computed as *core clock frequency* / GHz × *number of cache lines*
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*transferred fetched/stored per cycle* × *cache line size* (64 B).
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- DRAM bandwidths are computed as *DRAM transfer rate* [T/s] × *bus width* (64 B/T) ×
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- DRAM bandwidths are computed as *DRAM transfer rate* [T/s] × *bus width* (64 bit/T) ×
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*number of channels*.
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- TODO how is HBM bandwidth computed?
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- HBM bandwidth is computed as *HBM transfer rate* [T/s] × *bus width* (1024 bit/T) ×
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*number of HBM stacks*.
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## Peak system floating-point performance, theoretical
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