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Add SMT row authored by Moritz Beutel's avatar Moritz Beutel
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ASC-infrastructure.md
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......@@ -36,29 +36,30 @@ This wiki gives an overview of the various server machines offered by the ASC ch
## CPU architecture overview
| feature | Xeon E5504 | Xeon E5530 | Xeon E3-1585 | Xeon Silver 4110 | Xeon Gold 6130 | Xeon Platinum 8168 | Xeon Phi 7210 |
| --------------------------- | ----------- | ----------- | -------------- | ---------------- | -------------- | ------------------ | ---------------- |
| architecture | Nehalem | Nehalem | Skylake-H | Skylake-SP | Skylake-SP | Skylake-SP | Knights Landing |
| vector instructions | SSE4.2 | SSE4.2 | AVX2 | AVX-512 | AVX-512 | AVX-512 | AVX-512 |
| cores per socket | 4 | 4 | 4 | 8 | 16 | 24 | 64 |
| base frequency | 2.0 GHz | 2.4 GHz | 3.5..3.9 GHz | 2.1 GHz | 2.1 GHz | 2.7 GHz | 1.3 GHz |
| AVX2 frequency | | | 3.5..3.9 GHz | 1.7 GHz | 1.7 GHz | 2.3 GHz | 1.1 GHz |
| AVX-512 frequency | | | | 1.0 GHz | 1.3 GHz | 1.9 GHz | 1.1 GHz |
| L1 instruction cache | 32 KB | 32 KB | 32 KB | 32 KB | 32 KB | 32 KB | 32 KB |
| L1 data cache | 32 KB | 32 KB | 32 KB | 32 KB | 32 KB | 32 KB | 32 KB |
| L2 cache (per core) | 256 KB | 256 KB | 256 KB | 1 MB | 1 MB | 1 MB | 1 MB per 2 cores |
| L2 cache (per socket) | 1 MB | 1 MB | 1 MB | 8 MB | 16 MB | 24 MB | 32 MB |
| L3 cache type | inclusive | inclusive | inclusive | exclusive | exclusive | exclusive | |
| L3 cache (per core) | | | 2 MB | 1.375 MB | 1.375 MB | 1.375 MB | |
| L3 cache (per socket) | 4 MB | 8 MB | 8 MB | 11 MB | 22 MB | 33 MB | |
| eDRAM | | | 128 MB | | | | |
| HBM | | | | | | | 16 GB |
| L1 read bandwidth | | | 448..499 GB/s | 269 GB/s | 269 GB/s | 346 GB/s | 166 GB/s |
| L2 bandwidth | | | 224..250 GB/s | 135 GB/s | 135 GB/s | 173 GB/s | 83 GB/s |
| eDRAM bandwidth, ST | | | | | | | |
| eDRAM bandwidth, concurrent | | | | | | | |
| HBM bandwidth, ST | | | | | | | |
| HBM bandwidth, concurrent | | | | | | | |
| SSE2 GFlops/s | | | | | | | |
| AVX2 GFlops/s | | | | | | | |
| AVX-512 GFlops/s | | | | | | | |
| feature | Xeon E5504 | Xeon E5530 | Xeon E3-1585 | Xeon Silver 4110 | Xeon Gold 6130 | Xeon Platinum 8168 | Xeon Phi 7210 |
| --------------------------- | ----------- | ----------- | ------------------ | ---------------- | -------------- | ------------------ | ---------------- |
| architecture | Nehalem | Nehalem | Skylake-H | Skylake-SP | Skylake-SP | Skylake-SP | Knights Landing |
| vector instructions | SSE4.2 | SSE4.2 | AVX2 | AVX-512 | AVX-512 | AVX-512 | AVX-512 |
| cores per socket | 4 | 4 | 4 | 8 | 16 | 24 | 64 |
| SMT | | | 2 threads per core | | | | |
| base frequency | 2.0 GHz | 2.4 GHz | 3.5..3.9 GHz | 2.1 GHz | 2.1 GHz | 2.7 GHz | 1.3 GHz |
| AVX2 frequency | | | 3.5..3.9 GHz | 1.7 GHz | 1.7 GHz | 2.3 GHz | 1.1 GHz |
| AVX-512 frequency | | | | 1.0 GHz | 1.3 GHz | 1.9 GHz | 1.1 GHz |
| L1 instruction cache | 32 KB | 32 KB | 32 KB | 32 KB | 32 KB | 32 KB | 32 KB |
| L1 data cache | 32 KB | 32 KB | 32 KB | 32 KB | 32 KB | 32 KB | 32 KB |
| L2 cache (per core) | 256 KB | 256 KB | 256 KB | 1 MB | 1 MB | 1 MB | 1 MB per 2 cores |
| L2 cache (per socket) | 1 MB | 1 MB | 1 MB | 8 MB | 16 MB | 24 MB | 32 MB |
| L3 cache type | inclusive | inclusive | inclusive | exclusive | exclusive | exclusive | |
| L3 cache (per core) | | | 2 MB | 1.375 MB | 1.375 MB | 1.375 MB | |
| L3 cache (per socket) | 4 MB | 8 MB | 8 MB | 11 MB | 22 MB | 33 MB | |
| eDRAM | | | 128 MB | | | | |
| HBM | | | | | | | 16 GB |
| L1 read bandwidth | | | 448..499 GB/s | 269 GB/s | 269 GB/s | 346 GB/s | 166 GB/s |
| L2 bandwidth | | | 224..250 GB/s | 135 GB/s | 135 GB/s | 173 GB/s | 83 GB/s |
| eDRAM bandwidth, ST | | | | | | | |
| eDRAM bandwidth, concurrent | | | | | | | |
| HBM bandwidth, ST | | | | | | | |
| HBM bandwidth, concurrent | | | | | | | |
| SSE2 GFlops/s | | | | | | | |
| AVX2 GFlops/s | | | | | | | |
| AVX-512 GFlops/s | | | | | | | |